DS1821
 
13 of 19
Figure 9 illustrates that the sum of T
INIT
, T
RC
, and T
SAMPLE
 must be less than 15 ?/SPAN>s for a read time slot.  
Figure 10 shows that system timing margin is maximized by keeping T
INIT
 and T
RC
 as short as possible 
and by locating the master sample time during read time slots towards the end of the 15 祍 period.
 
READ/WRITE TIME SLOT TIMING DIAGRAM Figure 8 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
DETAILED MASTER READ 1 TIMING Figure 9 
 
 
 
 
 
 
 
 
 
RECOMMENDED MASTER READ 1 TIMING Figure 10
 
V
DD
 
GND
1-WIRE BUS
15 ?/SPAN>s
VIH of Master
T
RC
 
T
INT
 > 1 ?/SPAN>s
Master samples
V
DD
 
GND
1-WIRE BUS
15 ?/SPAN>s
VIH of Master
T
RC
=
T
INT
 =
small
 
Master samples
LINE TYPE LEGEND (Figure 8, Figure 9 and Figure 10)
Bus master pulling low
 
DS1821 pulling low
 
 
Resistor pullup
45 ?/SPAN>s  
15 ?/SPAN>s  
V
DD
 
GND
1-WIRE BUS
60   s < T
X
 0 < 120
1 ?/SPAN>s < T
REC
 <  
DS1821 samples
15 ?/SPAN>s  
30 ?/SPAN>s  
> 1 ?/SPAN>s 
MASTER WRITE 0 SLOT 
MASTER WRITE 1 SLOT 
DS1821 samples
V
DD
 
GND
1-WIRE BUS
15 ?/SPAN>s  
MASTER READ 0 SLOT 
MASTER READ 1 SLOT 
Master samples 
Master samples 
START
OF SLOT 
START
OF SLOT 
> 1 ?/SPAN>s 
1 ?/SPAN>s < T
REC
 <  
15 ?/SPAN>s  
15 ?/SPAN>s  
30 ?/SPAN>s  
15 ?/SPAN>s  
> 1 ?/SPAN>s 
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